Opella-ARC Entry level Emulator
Entry-level Emulator and Source Debugger for ARC™ embedded systems

Ashling’s OPELLA-ARC EMULATOR is a powerful JTAG Emulator for embedded development with ARC International’s ARC™ configurable RISC cores.

OPELLA debugging is completely non-intrusive and requires no target system resources.

Together with ARC’s SEECODE source debugger, OPELLA provides powerful run/stop control of embedded software, with hardware and software breakpoints.

OPELLA provides fast code download to the target ARC™ system, and allows control and interrogation of all core-processor and system resources.

OPELLA connects to the host PC via a standard USB high-speed connection.

OPELLA supports FPGA Programming on ARC FPGA targets or user’s target board.

Developed in cooperation with ARC International plc, the OPELLA-ARC Emulator integrates with ARC’s SeeCode Source Debugger and High-C++ code development environment.

System Specification

Used together with the SeeCode Debugger, Opella-ARC provides a complete Emulation, Code-download, Source Debugging and FPGA programming workbench for development of embedded systems based on the ARC™ Configurable RISC Cores.

A self-configuring USB port on Opella-ARC ensures a reliable, easy-to-install high-speed connection to the host debugging PC.

A JTAG cable connects Opella-ARC to the target FPGA-prototype, ARC™ prototyping platform or final-silicon ARC-core device.

Opella-ARC Emulator Specification

• Fast application-code download using USB 1.1 connection
• Automatic sensing of target operating voltage; support for low voltage target systems
• Target Reset control and Remote Reset detect
• Run/stop control of target application including go, halt, step over, step into and step out of
• Operates with ARC’s SeeCode Debugger
• Support for Multi-core debug
• Support for multiple Opella connected to the same PC (this supports Multi-core systems where each core has a unique JTAG interface)
• All Windows hosts supported
• Display/read/write of target system memory and peripheral registers
• Support for all on-chip hardware breakpoints; unlimited software breakpoints
• ARCangel™ Development Board System FPGA programming support; allows easy configuration using an Opella connection between your host PC and ARCangel™
• All ARCtanget-A4, ARCtanget-A5, ARC 600 and ARC 700 cores are supported.
• Supports 1.8V, 2.5V, 3.3V and 5V target systems
• Opella is powered by USB port (Opella consumes 120mA from USB); a Universal DC power supply for independent powering is also included
• Supplied with 20-pin .1” Target Probe Assembly for Debug interface to target device or target FPGA.
• Optional 15-pin D-Type JTAG Target Probe Assembly for Debug interface to target device or ARCangel board.

Product Configuration

• Opella-ARC emulator
• Ashling Opella-ARC DLL software driver (for connection to SeeCode debugger)
• Ashling installation diagnostic software
• 20-pin Target Probe Assembly
• USB cable, universal power supply and documentation
• Optional 15-pin JTAG debug probe cable