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Ashling ARC™ Tools Accelerated!
ASHLING PRESS ANNOUNCEMENT
Limerick,
Ireland, November 2005:
In cooperation with ARC International, Ashling Microsystems has released the latest version of the Opella-USB emulator drivers that operates with ARC's SeeCode Debugger, ARCangel™ prototyping system and ARC core ASICs/SoCs to provide a full multi-core debugging platform for ARC applications including those based on ARC 600, ARC 700, ARCtangent-A4 and ARCtangent-A5 cores. This is a milestone release which dramatically increases the performance of Opella-USB for ARC.
During the debugging stage, ARC developers will frequently update their application to fix bugs as they are found. This "update" cycle typically consists of finding the bug, changing the associated source-code, rebuilding the application and downloading it to the target to allow retest. Application sizes for ARC applications can range from 10's of KB/s up to 10's of MB/s, hence, fast download to the target is essential to ensure the debugging stage can progress quickly.
Advantages of Opella
USB connection to host PC
Opella connects to the host PC using a compact and convenient USB link.
High-speed code communication to target
Opella incorporates a USB link for high-speed communication to the target, for both code download and FPGA "blasting". Using a 24MHz JTAG clock, Opella downloads to the target at approximately 584KB/s and reads-back data from the target at approximately 182KB/s.
Full control of JTAG communication clock
Opella offers a choice of JTAG clock speeds for debug-communications to the target ARC processor.
Full Multi-Core Debug support
Opella offers full support for multi-core target systems (where the ARC processors are on the same JTAG chain). In addition, multiple Opellas can be connected to a single PC for multi-core target systems with a unique JTAG chain for each ARC processor.
Readymade Debug Probes
Opella is supplied with a D15 debug probe cable, preconfigured for use with ARC International's ARCangel prototyping system; in addition, probe options (D20) are available for direct connection to the ARC processor (in a custom FPGA or in final silicon) on the user's target board.
Benefits of Opella as a debug platform
Taken together, the performance advantages of Opella mean that it is the recommended vehicle for real-time debugging on ARC systems, with benefits that include:
- Plug-and-play installation, with a convenient Setup program and USB auto-detect, ensures that installation time is minimized.
- High-speed download minimizes time lost when downloading large code images or FPGA configurations.
- Choice of JTAG clock speeds (24MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz, 2MHz and 1MHz) ensures reliable performance with high-speed and low-speed target systems.
- No problems with low-voltage targets: Opella's 20-pin target probe cable automatically adapts to target logic levels in the range 1.8V to 5.0V.
- Powerful Diagnostic utilities to confirm target JTAG communications, ARC processor (register) access and target memory access.
- Fully engineered Target Probes, with complete interface documentation, provide plug and-play operation when debugging on ARCangel prototyping system, on a custom FPGA implementation and on final custom silicon.
- Access to Ashling's ARC Engineering team for support.
The latest Opella for ARC drivers (v1.0.8) are available for download at www.ashling.com/support/ARC/ by registered users of Ashling's Software Update and Support Service.
For more details on Ashling's ARC tools, please visit our website at http://www.ashling.com/datasheets/arctools.html
