Hardware Debug and Trace Probes
Ashling have over thirty years’ experience in developing tools for embedded systems engineers including high-speed Debug and Trace Probes supporting a broad range of MCUs, SoCs and Soft (FPGA) based designs. We have developed “best-in-class” probes for several different vendors based on the following on-chip debug and trace standards:
- JTAG (IEEE 1149.1) and cJTAG (IEEE 1149.7).
- IEEE-ISTO Nexus 5001 Trace.
- MIPI Alliance Debug.
- Arm CoreSight™ including Serial Wire Debug (SWD), JTAG, Trace (ETM, STM, PTM etc.) and Cross Triggering (CTI).
- RISC-V Debug and Trace (including both IEEE-ISTO Nexus 5001 and E-Trace standards).
- Synopsys ARC cJTAG/SWD/JTAG and IEEE-ISTO Nexus 5001 Trace.
- MIPS EJTAG, PCTRACE, PDTRACE and OCI Debug.
Opella-XD Debug Probe
All Ashling Hardware Debug and Trace Probes work with RiscFree™, Ashling’s Eclipse-CDT based Integrated Development Environment (IDE) and Debugger. GNU GDB and other third-party debuggers are also supported. Contact Ashling for more details.
Ashling Debug Probes
Ashling Debug Probes include the high-performance Opella-XD and the entry-level, OpenOCD compliant, Opella-LD. Both probes provide a universal hardware platform for all popular target architectures including Arm, MIPS, RISC-V and Synopsys ARC and support multi-core heterogeneous and homogeneous debug.
Ashling Trace Probes
Ultra-XD Debug and Trace Probe
Vitra-XD Debug and Trace Probe
- High-speed gigabit Ethernet/USB host interfaces.
- World’s fastest trace capture rates:
- Parallel (up to 16-bits) trace at to 400MHz double-data rate (DDR) or 800MHz single-data rate (SDR).
- Serial Gigabit trace – up to 4 lanes supported at speeds of up to 25.6Gb/s divided by number of lanes e.g. 6.4Gb/s for 4 lanes.
- Captured data can be independently time-stamped using a 50-bit, 5ns resolution timestamp generator.
- Large trace storage:
- 4GB on-board trace storage memory which may be configured as a circular buffer.
- “Streaming” support to host PC for unlimited storage.
- Automatic trace clock/data skew adjustment (“AUTOLOCK”) to ensure integrity of captured high-speed data; the Ashling Trace Probe can automatically calibrate itself to your target’s trace data port.
- Multi-core heterogeneous and homogeneous debug support (see here for more details).
- Universal hardware platform providing off-chip trace support for all popular target architectures including Arm, MIPS, RISC-V and Synopsys ARC.