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White paper on adding custom RISC-V Instructions to QEMU by Hugh O’Keeffe…
February 25, 2021 – LIMERICK, IRELAND. Ashling’s VP of Engineering Hugh O’Keeffe has written a new white-paper with a step-by-step guide on how to add custom RISC-V instructions to the QEMU emulator including how to build and debug applications which use the new custom instructions. See here…
Code Coverage Tool for RISC-V and Arm from Ashling…
February 8th, 2021 – LIMERICK, IRELAND.Ashling announces immediate availability of an integrated Code Coverage Tool for Arm and RISC-V based target applications within Ashling’s RiscFree™ IDE and Debug solution. Identifying untested code is an essential part of any software test plan and an automated means of recording the coverage of source code during unit test execution is either required or recommended by many software engineering standards. Measuring code coverage – the percentage of the overall software system…
Heterogeneous Multicore Debug Paper by Róisín O’Keeffe…
December 16th, 2020 – LIMERICK, IRELAND. Over the last decade there has been a dramatic increase in the number of multicore designs in embedded electronic SoC (System-on-Chip) devices. This drive towards multicore SoC designs was primarily driven by a desire for improved power consumption, cost, performance criteria, smaller form factors and concurrent application requirements. Combining several cores into a single device can reduce the number of components in the end-product thereby lowering…