Multi-Core Debugging

Ashling Multi-Core Debug

Today, System-on-Chip (SoC) design is becoming more complex as chip designers pack more and more features on to a single device to meet market demands including features, performance and power-consumption requirements.  

As process technology improvements reach their limits (the end of Moore’s law), designers are moving to multi-core designs and are now integrating processor architectures from different companies (i.e. heterogeneous cores) onto a single SoC.  It is now becoming common to find SoCs with multiple disparate cores from vendors such as ARM, ARC (Synopsys), MIPS (Wave Computing) and RISC‑V.

Ashling’s RiscFree™ IDE and Debugger provides a full Multi-Core Heterogeneous solution today all from within a single software environment using a single debug probe. Support is currently available for RISC-V, Synopsys ARC, ARM and (coming soon) Wave Computing MIPS cores.

A single Ashling Opella-XD Debug Probe can simultaneously debug multiple-cores using RiscFree™

The RiscFree™ IDE and Debugger allows full specification of your SoC core configuration and supports mixing and matching of cores from RISC-V, Synopsys ARC, ARM and Wave Computing MIPS cores. JTAG and ARM Coresight core debug interfaces are supported.

RiscFree™ debugging a multi-core design consisting of RISC-V and Synopsys ARC cores

The RiscFree™ Debugger shows dedicated views for each SoC core and these can be easily switched between (or “pinned” for permanent display).

RiscFree™ showing a dedicated, core-specific Register window for each SoC core