RiscFree™ is Ashling’s Eclipse-based Integrated Development Environment (IDE) for Arm and provides a complete, seamless environment for Arm software development.
Ashling ARM Solutions
RiscFree™ for Arm
- Eclipse based IDE with full source and project creation, editing, build and integrated debug support
- Automatic source-code formatting, syntax colouring and function folding
- RiscFree™ includes a single-shot installer that installs and automatically configures all the component tools to work “out‑of‑the‑box”.
- Project wizards and examples allowing you to quickly create projects from scratch or use the pre-built examples
- Full compiler toolchain including an optimising C/C++ compiler, assembler and linker including start-up code and run-time‑libraries.
- Hardware debug and trace probe options available for use with RiscFree debugger enabling hardware debug and trace
- Homogeneous and heterogeneous multi-core debug support
- ROM or RAM based debugging support (e.g. hardware breakpoints for flash-based support)
- High-level Register Viewer (XML database driven)
- RTOS debug support
- Serial Terminal window
- Script language for automating debugging sessions
Ashling’s Opella-XD-ARM is a high-speed Debug Probe for embedded development on Arm Cortex cores. Opella-XD-ARM works with Ashling’s PathFinder debugger and third-party debuggers. A GDB server driver is also provided allowing Opella-XD to work with the open-source GDB-based debugger and Eclipse CDT.
- Support for 1kHz to 100MHz JTAG clock
- Up to 3MB/s high speed download
- Supports all popular Arm cores
- Wide target voltage range: 0.9V to 3.6V
- Works with Windows and Linux hosts
Ashling’s Vitra-XD-ARM is a powerful, high-speed, high capacity 500GB Trace Probe supporting Arm Cortex cores. The long duration real-time trace data collection is crucial for safety and performance critical applications where tracing must be entirely non-intrusive.
- High capacity trace storage for Arm Cortex cores
- Enormous 500GB on-board trace buffer
- Long duration real-time trace data collection
- High speed parallel trace for fastest Arm based processors (trace port speeds up to 400MHz DDR)
- Serial Gigabit trace (Arm HSSTP) with up to 4 lanes supported at speeds of up to 25.6Gb/s
- 50-bit, 5ns resolution timestamp generator
- Automatic trace clock/data skew adjustment to ensure the integrity of captured high-speed data
- Fine-grained adjustment of JTAG clock frequency from 1kHz to 150MHz
- USB 2.0 and Gigabit Ethernet host interfaces
- Facilitates non-instrumented and non-intrusive performance analysis and code coverage analysis