RiscFree “Best-In-Class” IDE and Unified Debugger for Intel FPGAs.
- Developed by Ashling for Intel.
- Full toolchain including Ashling’s RiscFree for Intel FPGAs IDE, Compiler, Debugger and Trace.
- Works “out-of-the-box” and installed along with the Intel Quartus® FPGA Design Software.
- Provides software development and debug support for Nios V 32-bit and 64-bit (coming soon) soft processors based on the RISC-V ISA.
- Custom instruction support and extensions for the Nios V processor.
- Supports Intel Agilex, Stratix 10, Arria 10 and Cyclone 10 GX FPGA devices.
- Project Manager and Build Manager including Make and CMake support with rapid import, build and debug of Intel Quartus created application frameworks.
Figure 1. RiscFree Debugger
- Targeted Nios V GCC compiler toolchain fully integrated into the RiscFree IDE with support for newlib & picolibc run-time libraries using the Nios V Hardware Abstraction Layer (HAL)
“Different Cores, One Solution.” A single instance of RiscFree supports simultaneous (“Unified”) debugging of any number of heterogeneous or homogeneous Intel FPGA cores including Nios V and Arm.
- Run-time Debug using the Intel FPGA Download Cable II (USB Blaster II).
- Register Visualization for Nios V and Arm cores.
- Heterogeneous and homogeneous simultaneous multi-core debug support for Nios V and Arm cores.
- Zephyr, FreeRTOS and μC/OS RTOS debug awareness.
- Full target Linux OS (multi-core/multi-hart) kernel, device driver and application debug support.
- Real-time Trace (on-chip and off-chip) support for both Nios V and Arm cores. Off-chip trace requires the Ashling Vitra trace probe available from Ashling.
- Intel’s Simics Nios V simulator support.
Figure 2. RiscFree Debug Launch
*Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.