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Ashling’s RiscFree™ Breakthrough Solution for Heterogeneous, Multi-Core SoC Software Development supporting RISC-V…
RISC-V Summit, December 9th, 2019 – San Jose, CA. Ashling, a leading provider of embedded development tools today announced full support in Ashling’s RiscFree™ IDE and Debugger for Multi-Core Heterogeneous Software Development all from within a single software environment using a single debug probe.The RiscFree™ IDE and Debugger allows full specification of your SoC core configuration and supports cores from RISC-V, Synopsys ARC, ARM and (coming soon) Wave Computing MIPS. JTAG, CJTAG and ARM SWD Core…
Ashling’s RiscFree™ Toolchain now supports Western Digital’s SweRV RISC-V Cores
September 24th 2019 – Redwood Shores, CA. Ashling, a leading provider of embedded development tools announced today full tools support for Western Digital’s RISC-V open source SweRV cores on their RiscFree™ Toolchain. Western Digital’s RISC-V open source SweRV Core is a 32-bit, 2-way superscalar, 9 stage pipeline core offering compelling capabilities for embedded devices supporting data-intensive edge applications such as storage controllers and industrial IoT. RiscFree™ is Ashling’s Eclipse-based Integrated Development…
Ashling to present MATLAB™ Plugin at Synopsys ARC Processor Summit September 19th, 2019
August 14th, 2019 – Limerick, Ireland. Ashling today announced a new strategic collaboration with Synopsys Inc., which provides a Plugin allowing use of the MathWorks MATLAB and Simulink tools with the Synopsys DesignWare MetaWare Development Toolkit. The Ashling developed Plugin allows users to compile MATLAB/Simulink-generated C code using the MetaWare Development Kit resulting in code highly optimised for running on Synopsys DesignWare ARC processors particularly those with DSP extensions…