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Heterogeneous Multicore Debug Paper by Róisín O’Keeffe…
December 16th, 2020 – LIMERICK, IRELAND. Over the last decade there has been a dramatic increase in the number of multicore designs in embedded electronic SoC (System-on-Chip) devices. This drive towards multicore SoC designs was primarily driven by a desire for improved power consumption, cost, performance criteria, smaller form factors and concurrent application requirements. Combining several cores into a single device can reduce the number of components in the end-product thereby lowering…
New low-cost Opella-LD Debug Probe now available from Ashling…
December 4th, 2020 – LIMERICK, IRELAND. Ashling, Ashling announces immediate availability of Opella-LD, a new low-cost hardware Debug Probe for embedded development.Opella-LD supports debug of target architectures based on Arm, RISC-V or Synopsys ARC cores.
It supports JTAG, cJTAG and SWD interfaces and is OpenOCD compatible. Opella-LD can be used together with either Ashling’s RiscFree™ Eclipsed-based IDE/Debugger or the GNU GDB Debugger. Ashling provides a dedicated support page…
Execution Profiling Tool for RISC-V and ARM from Ashling…
November 9th, 2020 – LIMERICK, IRELAND. Ashling announces availability of an integrated Code Execution Profiling Tool for Arm and RISC-V based applications within Ashling’s RiscFree™ IDE and debug solution. Execution Profiling is a critical tool enabling optimisation and speed improvements in embedded applications. The tools allow developers to determine where the application computing time is spent allowing them to focus their optimisation and speed-improvement efforts on the program areas which…