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Ashling exhibiting at the Synopsys Processor IP Summit, Santa Clara, September 5th
August 29, 2024 Limerick, Ireland. Ashling will be attending the Synopsys Processor IP Summit in Santa Clara where we’ll be showcasing our latest embedded development tools & solutions, including support for the new Synopsys ARC-V (RISC-V based) Processor IP…
Microchip Technologies’ PIC64GX Quad-Core RISC-V-based MPU is now supported by Ashling’s RiscFree™ C/C++ SDK…
July 23, 2024 Limerick, Ireland. Embedded tools developer Ashling is pleased to partner with Microchip Technology, supporting the new and innovative PIC64GX RISC-V based multicore MPUs with our RiscFree™ C/C++ SDK and Opella-XD Debug Probe.
Ashling announces RiscFree™ C/C++ SDK support for India’s C-DAC VEGA RISC-V-based Multi-core Microprocessors…
July 8th, 2024 Kochi, India. Embedded tools developer Ashling is pleased to partner with C-DAC, supporting their VEGA RISC-V based multi-core microprocessor family with our RiscFree™ C/C++ SDK and Opella-XD Debug Probe…
Ashling welcomes Ravindra Nuguri as Strategy and Business Development Advisor…
June 20, 2024 Limerick, Ireland. Ashling, a leader in embedded tools and services for the semiconductor industry, is pleased to announce the appointment of Ravindra (“Ravi”) Nuguri as Strategy and Business Development Advisor…
Ashling and Embecosm to Accelerate RISC-V Vector QEMU Emulation…
May 24, 2024 Limerick, Ireland. Ashling and their partner Embecosm announced today that they are working with the RISE (RISC-V Software Ecosystem) Project to optimize RISC-V vector instructions emulation for QEMU the open-source emulator. Our joint goal is to ensure that RISC-V vector instructions powered binaries run at rocket 
speed under QEMU by mapping the RISC‑V vector instructions to the best hardware equivalents on the host, leveraging up to 256-bit SIMD vectors for maximum performance.