Global organizations trust Ashling to provide products and services for their business-critical operations.
Ashling’s RiscFree™ now supports Western Digital’s SweRV EH2 and EL2 RISC-V Cores…
July 9, 2020 – Redwood Shores, CA and Limerick, Ireland. Ashling a leading provider of embedded development tools announced today full tools support for the latest Western Digital’s RISC-V open source SweRV EH2 and EL2 cores on their RiscFree™ Toolchain.Western Digital’s RISC-V open source SweRV now has two new additions EH2 and EL2 which are both available to the open-source community. EH2 is a high-performance 32-bit, dual-thread, superscalar, 9-stage pipeline core with simulated performance of up to 6.3 CoreMark/MHz…
As a member of the OpenHW Group, Ashling will work together with the OpenHW Group engineering team to provide…
March, 2020 – Limerick, Ireland. A current OpenHW Group project, called the “CORE-V Chassis SoC”, includes the CORE-V family of open-source RISC-V cores including a Linux capable 64-bit processor coupled with a 32-bit coprocessor. OpenHW aims to tape out a heterogeneous multi-core processor evaluation SoC, capable of running the Linux operating system during the 2nd half of 2020. Ashling development tools are currently available for a range of RISC-V based processors. In addition, Ashling’s RiscFree IDE supports heterogeneous multicore…
Ashling’s RiscFree™ Breakthrough Solution for Heterogeneous, Multi-Core SoC Software Development supporting RISC-V…
RISC-V Summit, December 9th, 2019 – San Jose, CA. Ashling, a leading provider of embedded development tools today announced full support in Ashling’s RiscFree™ IDE and Debugger for Multi-Core Heterogeneous Software Development all from within a single software environment using a single debug probe.The RiscFree™ IDE and Debugger allows full specification of your SoC core configuration and supports cores from RISC-V, Synopsys ARC, ARM and (coming soon) Wave Computing MIPS. JTAG, CJTAG and ARM SWD Core…