June 21, 2022 – Ashling, a supplier of high-performance embedded software and hardware tools for the RISC-V market and Embecosm the leading supplier of RISC-V free and Open-source Compiler Toolchains today announced their partnership, now in its fifth year, continues to grow and deliver the full spectrum of development tools including Compilers, IDEs, Debuggers, SDKs and Debug and Trace probes to a broad range of customers particularly in the RISC-V market.

Read the official press-release here.

May 31, 2022, Silicon Valley, CA and Arlington, VA Ashling and CAES announced today that Ashling’s RiscFree Toolchain will provide software development support for CAES’ NOEL-V fault tolerant RISC-V based processors. NOEL-V is a synthesizable VHDL processor model based on the open RISC-V architecture targeting mission critical electronics for aerospace and defense industries. Seven different configurations are now available, ranging from a tiny 32-bit version to a 64-bit high performance version. NOEL-V complements the LEON line of processors and is suitable for fault and radiation-tolerant FPGAs and ASIC designs for space and satellite applications…

May 30, 2022, Silicon Valley, California, USA. Ashling and GigaDevice Semiconductor jointly announced today that Ashling’s RiscFree Toolchain for RISC-V will provide specific software development support for GigaDevice’s GD32V series of RISC-V based microcontrollers (GD32V). The GD32V device is a 32-bit general-purpose microcontroller based on the RISC-V core with an impressive balance of processing power, reduced power consumption, and peripheral set. GD32V devices are suitable for a wide range of interconnected applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems…

May 23rd, 2022, Silicon Valley, Calif. USA – Ashling announced today that Ashling’s RiscFree Toolchain for RISC-V will provide specific software development support for Microchip Technology’s PolarFire SoC RISC-V-based processors. The PolarFire SoC FPGA family delivers a combination of low power consumption, thermal efficiency and defense grade security for smart, connected systems and is the first system on chip (SoC) field-programmable gate array (FPGA) with a deterministic, coherent RISC-V CPU cluster and …

“Open-source” Hardware Design…

14th Feb 2022, Limerick, Ireland. The OpenHW Group are taking open-source principles that have revolutionised the software industry and applying them to hardware design in the development of a family of RISC-V based microprocessor cores (“CORE-V”). We’re proud to be part of the group and as of now we are involved in the Software Development Toolchain and SDK for CORE-V. OpenHW is part of the Eclipse Foundation community and you can find more details here…

SAN FRANCISCO, CA USA – RISC-V Summit 2021. Ashling and Andes Technology announced today that Ashling’s RiscFree™ Toolchain will be extended to support the broad range of Andes RISC-V CPU IPs including support for the AndeStar™ V5 Performance and CoDense™ ISA Extension, leveraging the high-quality and production-proven Andes GNU compiler.

RiscFree™ is Ashling’s Integrated Development Environment (IDE), Compiler and Debugger for RISC-V based development and now adds support for Andes RISC-V CPUs including the 32-bit: N22, N25F, D25F, A25, A25MP,A27, A27L2, N45, D45, A45 & A45MP and the 64-bit: NX25F, AX25, AX25MP, NX27V, AX27, AX27L2, NX45, AX45 & AX45MP…