Global organizations trust Ashling to provide products and services for their business-critical operations.
Ashling RiscFree™ now supports Andes Technology RISC-V CPUs…
SAN FRANCISCO, CA USA – RISC-V Summit 2021. Ashling and Andes Technology announced today that Ashling’s RiscFree™ Toolchain will be extended to support the broad range of Andes RISC-V CPU IPs including support for the AndeStar™ V5 Performance and CoDense™ ISA Extension, leveraging the high-quality and production-proven Andes GNU compiler.
RiscFree™ is Ashling’s Integrated Development Environment (IDE), Compiler and Debugger for RISC-V based development and now adds support for Andes RISC-V CPUs including the 32-bit: N22, N25F, D25F, A25, A25MP,A27, A27L2, N45, D45, A45 & A45MP and the 64-bit: NX25F, AX25, AX25MP, NX27V, AX27, AX27L2, NX45, AX45 & AX45MP…
Ashling RiscFree™ now supports Alibaba’s RISC-V CPUs…
SAN FRANCISCO, CA USA – RISC-V Summit 2021 – Ashling announced today that Ashling’s RiscFree™ Toolchain will be extended to support the broad range of Alibaba RISC-V CPU IPs including support for the open source XuanTie E902, E906, C906, and C910.
RiscFree™ is Ashling’s Integrated Development Environment (IDE), Compiler and Debugger for RISC-V based development and now adds support for Alibaba RISC-V CPUs including the 32-bit and the 64-bit cores…
Ashling announce plans for OpenHW CORE-V Development Kit…
November 2nd, 2021 – Silicon Valley. The OpenHW CORE-V (https://www.openhwgroup.org/) group are currently developing a range of open-source, RISC-V ISA based cores known as CORE-V.
Ashling, as an OpenHW member, are actively involved in working on the definition and implementation of a CORE-V Development Kit which includes a reference board designed around a CORE-V MCU and an SDK containing everything needed to develop software to run on the board….