This page provides information and software downloads for Ashling’s RiscFree™ for RISC-V IDE and Opella-XD for RISC-V Debug Probe.
Please contact our Technical Support team if you need help on Ashling hardware or software tools.
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RiscFree™ for RISC-V, v1.2.9, 9th September 2020
New Features in this release
- Includes PDF documentation (APB222-RiscFree.pdf). Please read this to get started
- Homogeneous multi-core debug support from a single launch (non-stop and all-stop).
- Heterogeneous debug support for RISC-V and non-RISC-V cores
- SoC-wide breakpoint support i.e. a single breakpoint can halt ALL cores
- Enhanced synchronization for multiple active launches using a single Opella-XD probe.
- Support for RiscFree Command line invocation
> riscfree.exe -data <workspace path> -launch <launch configuration file name> - RiscFree launch supports Eclipse environment variable (e.g.: ${eclipse_home}).
- Register View includes bit-level information
- Opella-XD JTAG frequency selection supports 10kHz – 100MHz