Opella-LD Debug Probe

Overview

Ashling’s Opella-LD is Ashling’s low-cost Debug Probe for embedded development with support for multiple target architectures including Synopsys ARC, Arm and RISC-V powered systems.

opella-ld

Figure 1. The Ashling Opella-LD Debug Probe

Opella-LD software debug support is provided via the open-source OpenOCD (http://openocd.org/doc/html/About.html) standard and provides fast code download to the target system with control and interrogation support for all core-processor and system resources including registers and memory. OpenOCD allows debugging via Ashling’s RiscFree™ Eclipsed based IDE and Debugger and the GNU GCC GDB debugger.

Opella-LD features

  • Low-cost, compact form-factor
  • Works with Synopsys ARC, Arm and RISC-V powered systems
  • Works under Windows and Linux with a USB Type-C host PC interface
  • Supports JTAG, cJTAG and SWD debug interfaces with up to 30MHz data clock rates
  • Four LEDs to indicate Power, Target Present, JTAG or SWD mode and Data Transfer Activity
  • Supports and automatically adapts to target voltages between 0.9v and 5.0v
  • Supports JTAG TAP Reset (TRST) and System Reset (SRST)
  • Dedicated www.ashling.com/Opella-LD/ site with latest user documentation, drivers and OPENOCD configuration files for all target architectures
  • Opella-LD is provided with “flying-leads” allowing easy connection to your target. Dedicated adapters are also available for standard target foot-prints such as MIPI/Arm Coresight 10-way.